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[Other resource] jtag_cpld_vhdl

Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。 以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。 -JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: | Size: 2023 | Author: 李伟 | Hits:

[WEB Code] jtag_logic

Description: USB下载线的vhdl程序,实现USB协议和JTAG接口的转换,用状态机实现的
Platform: | Size: 2517 | Author: 一王 | Hits:

[VHDL-FPGA-Verilog] usb_jtag

Description: FPGA、CPLD芯片的usb数据下载线，下载速度是并口的5位，内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
Platform: | Size: 234496 | Author: 李聚光 | Hits:

[VHDL-FPGA-Verilog] presentation_pfe_v3.6.ppt

Description: Jtag communication design with VHDL script
Platform: | Size: 1478656 | Author: Marwen | Hits:

[VHDL-FPGA-Verilog] VGA

Description:
Platform: | Size: 1262592 | Author: 一天 | Hits:

[VHDL-FPGA-Verilog] Oscilloscope

Description: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable.
Platform: | Size: 1854464 | Author: sami | Hits:

[VHDL-FPGA-Verilog] Quartus_II_Project

Description:
Platform: | Size: 477184 | Author: 陶宇 | Hits:

[VHDL-FPGA-Verilog] JTAG_timing

Description: 用VHDL实现的JTAG时序，其中有16个状态机来控制产生该时序。-jtag timing implemented by VHDL
Platform: | Size: 34816 | Author: liuqi | Hits:

[VHDL-FPGA-Verilog] JTAG_CPLD_project_1.pdf

Description: JTAG_CPLD_project source VHDL code ，适用于开发JTAG接口。此工程使用Altera EPM570 MAX II CPLD，包含硬件和软件描述。-JTAG_CPLD_project source VHDL code, suitable for the development of the JTAG interface. This project using the Altera EPM570 MAX II CPLD, includes hardware and software description.
Platform: | Size: 1273856 | Author: Jeff_Cai | Hits:

[VHDL-FPGA-Verilog] jtag_master.tar

Description: JTAG模块的VHDL代码，用于了解JTAG内部结构原理，可集成嵌入IC,为IC提供JTAG功能。十分强大的代码，方便可靠。-VHDL code JTAG module is used to understand the internal structure principle JTAG can be integrated embedded IC, the IC provides JTAG functionality. The code is very powerful, convenient and reliable.
Platform: | Size: 3072 | Author: 倪潇飞 | Hits:
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